The present invention generally relates to semiconductor device manufacturing, and more particularly to fabricating a deep trench memory cell using a buffered sidewall image transfer technique.
Semiconductor device manufacturing generally includes various steps including a patterning process. For example, the manufacturing of a semiconductor chip may start with, for example, CAD (computer aided design) generated device patterns and may continue with the effort to replicate these device patterns in a substrate in which semiconductor devices can be formed. The replication process may involve the use of a photolithography process in which a layer of photo-resist material may be first applied on top of a substrate, and then be selectively exposed according to a pre-determined device pattern. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to a certain solution. Next, the photo-resist may be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern. The photo-resist pattern may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.
Engineers are continuously facing the challenge of how to meet the market demand for ever increasing device density. One technique for tight pitch patterning is to achieve nearly twice the pattern density through a technique called sidewall image transfer (SIT), also known as sidewall spacer image transfer. A typical SIT process can include lithographically forming a mandrel above a substrate from a photo-resist material or other suitable material. A material suitable for forming sidewall spacers is subsequently deposited on top of the mandrel and to eventually form sidewall spacers next to the mandrel. The mandrel can then be removed selective to the sidewall spacers and the remaining sidewall spacers can define the desired device pattern. The device pattern defined by the sidewall spacers may generally be transferred into the substrate. The SIT technique may be used to produce the fins for multiple fin field effect transistors (hereinafter “finFET”) within a finFET device region. Typically, regions of a wafer not designated as the finFET device region may be recessed below a top surface of the fins. The regions of the wafer not designated as the finFET device region may be designated as a planar device region.